Gate driving devices of this type have been proposed having various configurations, such as for example those described in Japanese Patent Application Laid-open No. 2008-291728 and Japanese Patent Application Laid-open No. 2010-288444.
Japanese Patent Application Laid-open No. 2008-291728 discloses a device which uses an IGBT to control the current flowing in primary-side windings to control ignition by a plug connected to the coil secondary-side windings, and achieves both reduced turn-on voltage for low battery voltages and a sufficient conduction start time.
Japanese Patent Application Laid-open No. 2010-288444 discloses a gate driving device in which, as shown in FIG. 11, the load is taken to be an inductance L, and the gate of an IGBT or other active element having a current sensing function is driven by a control IC 4.
In the case of this gate driving device, the inductance L as the load and an IGBT 3 are connected in series between a power supply line 1 to which the power supply voltage Vbatt of a battery as an external power supply and a ground line 2 connected to ground gnd.
Further, the control IC 4, and a current-limiting resistor RB for when a voltage equal to or greater than the clamp voltage of the IC 4 is applied across A-B, are connected in parallel with the inductance L and IGBT 3. A current sense voltage Vsns output from a current sensing terminal s of the IGBT 3 is input to this control IC 4. The gate voltage Vg output from the control IC 4 is supplied to the gate of the IGBT 3.
Further, a noise elimination capacitor C1 which eliminates high-frequency noise from the inductance L is connected in parallel with the series circuit of the current-limiting resistor RB and control IC 4. A high-pass capacitor C2 is connected to the power supply line 1 and the ground line 2 in parallel with the control IC 4. L1 and L2 are the wiring inductances of the power supply line 1 and ground line 2.
FIG. 12 shows a specific configuration of a portion related to driving control of the IGBT 3 by the control IC 4 shown in FIG. 11.
As shown in FIG. 12, in the control IC 4, a constant-current source 5, P-type MOS transistor M1, and N-type MOS transistor M3 are connected in series between a power supply line 11 to which an internal power supply voltage Vdc0 is applied and a ground line 12 connected to ground gnd. A P-type MOS transistor for current control M2 is connected in parallel with the MOS transistor M3. Parasitic body diodes D1 to D3 are connected in parallel with the MOS transistors M1 to M3. The op-amp 6 and resistors R1 and R2 form an error amplifier, to control the gate voltage of the MOS transistor M2.
Using a control IC 4 configured in this way, the MOS transistors M1 and M3 are controlled to turn on/off by switch signals SWp, SWn synchronized with a control signal Sin input to the control IC 4 shown in FIG. 11, to control charging/discharging of the IGBT 3. That is, when the MOS transistor M1 is turned on the IGBT 3 is charged, and when the MOS transistor M1 is turned off the IGBT 3 is discharged.
The op-amp 6 controls the gate voltage of the MOS transistor M2 such that the current sense voltage Vsns obtained by using a sense resistor to convert the sense current input from the current sense terminal S of the IGBT 3 into a voltage is equal to the reference voltage Vref; by this means, the gate voltage Vg of the IGBT 3 is controlled to control the collector current Ic of the IGBT 3.
If the amplitude of the battery voltage Vbatt fluctuates as a result of battery ripple, the voltage across points A-B in FIG. 11 drops momentarily at the time the battery voltage Vbatt falls due to the resonance circuit formed by the wiring inductances L1 and L2 and the capacitor C1. The momentary drop in voltage gradually increases with increasing collector current Ic of the IGBT 3, and momentarily falls below the minimum operating power supply voltage of the control IC 4.
However, a bypass capacitor C2 is connected in parallel with the control IC 4, and a low-pass filter is formed by this bypass capacitor C2 and the current-limiting resistor RB. Through this low-pass filter effect, the voltage across the bypass capacitor C2 repeatedly undergoes gradual increases and decreases. Consequently the internal power supply voltage Vdc of the control IC 4 is held at a substantially constant voltage which sufficiently exceeds the minimum operating power supply voltage of the control IC 4.
When the bypass capacitor C2 is eliminated with the object of reducing the number of components, the low-pass filter effect can no longer be produced. Hence the voltage across points C-B of the control IC 4 shown in FIG. 11 assumes the same waveform as the voltage across points A-B. Consequently a momentary voltage drop occurs in the internal power supply voltage Vdc, and the gate voltage Vg of the IGBT 3 also undergoes a large momentary voltage drop. As a result a sharp change is imparted to the current Ic flowing in the IGBT 3, and an induced voltage proportional to the current change occurs in the inductance L which is the load.
There are two reasons for the momentary large voltage drop in the gate voltage Vg.
The first reason is that the relation between the internal power supply voltage Vdc of the control IC 4 and the gate voltage Vg temporarily changes to Vdc<Vg, and gate charge accumulated on the gate of the IGBT 3 flows out to the power supply line 11 via the parasitic body diode D1 of the MOS transistor M1. The second reason is that, if there is a sharp voltage drop during current-limiting control, gate charge which has accumulated on the gate of the IGBT 3 via the MOS transistor M2 flows out to the ground line 12.
Thus in order to eliminate the bypass capacitor C2, the above-described problems must be resolved; as a means of improvement, devices such as the control IC 4a shown in FIG. 13 are known (see Japanese Patent Application Laid-open No. 2010-288444).
As shown in FIG. 13, this control IC 4a has the basic configuration of the control IC 4 shown in FIG. 12, but further adds the following constituent elements.
That is, a parallel circuit inserted into the internal power supply line 11 and comprising a resistor R3 and a diode D11, and a voltage drop suppression circuit 80, are added. Further, a diode D12 connected in parallel with the series circuit of the constant-current source 5 and MOS transistor M1, and a resistor R4 inserted between the output terminal of the op-amp 6 and the gate of the MOS transistor M2, are added.
The voltage drop suppression circuit 80 comprises a low voltage detection circuit 8 which detects momentary voltage drops in the internal power supply voltage Vdc0, and a MOS transistor M4 which immediately turns off when the low voltage detection circuit 8 detects a voltage drop. A parasitic body diode D4 is connected in parallel with the MOS transistor M4.
In the control IC 4a configured in this way, when the amplitude of the battery voltage Vbatt fluctuates due to battery ripple, as a result momentary overshoot occurs in the internal power supply voltage Vdc0 of the control IC 4a at the time the voltage falls. This overshoot of the internal power supply voltage Vdc0 increases with increasing collector current Ic of the IGBT 3, and finally falls below the minimum operating voltage of the control IC 4.
That is, due to resonance between the wiring inductances L1 and L2 and the noise elimination capacitor C1, the terminal voltage Vab calls. Under this influence a state ensues in which the internal power supply voltage Vdc0 falls, and momentarily falls below the minimum operating voltage of the control IC 4a. 
However, the low voltage detection circuit 8 detects such a momentary voltage drop of the internal power supply voltage Vdc0, and immediately turns off the MOS transistor M4 based on this detection. Hence discharging of charge accumulated on the gate of the IGBT 3 to the ground line 12 via the MOS transistors M2 and M4 can be reliably prevented. As a result, the IGBT 3 can continue to operate in the on state.
On the other hand, when the internal power supply voltage Vdc0 is lower than the gate voltage Vg of the IGBT 3 due to a momentary drop in the internal power supply voltage Vdc0, charge which has accumulated on the gate of the IGBT 3 flows out to the power supply line 11 via the parasitic body diode D1 of the MOS transistor M1 (or the diode D12).
However, the parallel circuit of the diode D11 and the resistor R3 is inserted into the power supply line 11. Hence the diode D11 prevents the outflow of gate charge to the internal power supply circuit (not shown) connected to the power supply line 11. Further, the resistor R3 forms a low-pass filter with the capacitance of the gate of the IGBT 3, and so momentary movement of gate charge toward the internal power supply circuit is prevented, and in addition the minimum limiting current at which operation of the circuit connected to the internal power supply is possible is supplied.
As explained above, when a momentary voltage drop occurs in the internal power supply voltage Vdc0 within the control IC 4a shown in FIG. 13, outflow of gate charge from the IGBT 3 to the internal power supply circuit and outflow to the ground line 12 can both be reliably suppressed. Hence the IGBT 3 can hold the gate charge and suppress drops in the gate voltage Vg, and the internal power supply voltage Vdc on the downstream side of the parallel circuit of the diode D11 and resistor R3 in the control IC 4a can be held at a voltage slightly reduced from the voltage immediately before the drop in the internal power supply voltage Vdc.
Moreover, despite large fluctuations in the internal power supply voltage Vdc0, extremely small fluctuations in the internal power supply voltage Vdc can be suppressed and the internal power supply can be stabilized. Hence another purpose can be served of temporarily augmenting (supplying) the voltage for another circuit which uses the internal power supply voltage Vdc as a power supply.
However, in the control IC 4a shown in FIG. 13, when for example the power supply voltage is constantly at low voltage, it is no longer possible to ignore voltage drops across the point of supply of the internal power supply voltage Vdc0 of the power supply line 11 and the gate of the IGBT 3, and there is the possibility that the gate voltage Vg of the IGBT 3 may drop and the IGBT 3 can no longer be driven adequately.
On the other hand, a control IC 4b such as that shown in FIG. 14 has been proposed.
This control IC 4b adds a regulator circuit 7 to the configuration of the control IC 4a shown in FIG. 13. The regulator circuit 7 stabilizes the voltage Vbin across points C-B in FIG. 11, and outputs a stabilized voltage Vreg.
FIG. 15 shows a specific example of the low voltage detection circuit 8 shown in FIG. 14 (see Japanese Patent Application Laid-open No. 2010-288444).
As shown in FIG. 15, this low voltage detection (undervoltage detector) circuit 8 comprises a self-biased type comparator 81, connected between the internal power supply line 11 to which the internal power supply voltage Vdc is supplied and the ground line 12 connected to ground gnd.
The non-inverting input of this comparator 81 is connected to the connection point between a resistor R11 and an N-type MOS transistor M11, which are connected in series between the internal power supply line 11 and the ground line 12. The inverting input of the comparator 81 is connected to the connection point between a diode D31 and a resistor R13, which are connected in series between the line 13 to which the output voltage Vreg of the regulator circuit 7 is applied and the ground line 12.
A parallel circuit of an inverter 82, a resistor R14 and a diode D32 the cathode of which is on the side of the comparator 81 is inserted between the output side of the comparator 81 and the N-type MOS transistor M4, and a gate signal is output from this parallel circuit to the gate of the MOS transistor M4. C10 is the gate-emitter capacitance of the MOS transistor M4.
Next, an example of operation of the low voltage detection circuit 8 shown in FIG. 15 is explained, referring to FIG. 14 to FIG. 16.
As shown in FIG. 16(A), the voltage Vbin across points C-B in FIG. 11 is raised (increased) from the minimum value (0 V) to the maximum value, and upon reaching the maximum value, falls (decreases) to the minimum value.
This change in the voltage Vbin is accompanied by a rise in the output voltage Vreg of the regulator circuit 7 shown in FIG. 14 and the internal power supply voltage Vdc, while maintaining the relation Vreg>Vdc, as shown in FIG. 16(A); each reaches a constant value and maintains the constant value. Thereafter, each falls from the respective constant value to the minimum value.
This change is accompanied by a change in the input voltage V+ of the non-inverting input terminal (+) and the input voltage V− of the inverting input terminal (−) of the comparator 81 shown in FIG. 15, as shown in FIG. 16(B), and the input voltage V− is always higher than the input voltage V+. This is because the rise in the output voltage Vreg is earlier than that of the internal power supply voltage Vdc, and moreover the forward-direction voltage of the diode D31 is lower than the threshold voltage of the MOS transistor M11.
As a result the output CMPout of the comparator 81 goes to L level (low level), as shown in FIG. 16(C). In FIG. 16(C), where there is a minute voltage, an indeterminate state occurs at the rising or falling of the power supply.
The output of the comparator 81 is logically inverted by the inverter 82, and so the output of the inverter 82 is H level (high level). Hence the output voltage OUTB of the low voltage detection circuit 8 shown in FIG. 15 is always H level, as shown in FIG. 16(D), and is applied to the gate of the MOS transistor M4 shown in FIG. 14.
As a result, the drain current Id of the MOS transistor M4 is the current shown in FIG. 16(E). That is, in the state at which the power supply voltage is low (low power supply voltage state), the VREF potential, which ordinarily should be constant, falls, and together with this the charge which should have charged the gate of the IGBT 3 flows out to the ground line 12 via the MOS transistor M4 due to the operation of the op-amp 6, so that the voltage at the gate of the IGBT 3 falls. As a result, when in the low power supply voltage state, the current Ic flowing in the IGBT 3 is limited to a low current range.